The source files are tut4.tv, and ram1.v or ram1.vhd. The previous testbenches exercised a DUT with separate input and output buses; ram1.v has a bi-directional data bus. This DUT also has both sequential and combinatorial paths, and requires two drive declarations to test both, with different drive statements for a synchronous RAM write, and an asynchronous RAM read. The testbench also demonstrates the use of macros.
The expected output is:
(Log) (340 ns) 34 vectors executed (18 passes, 0 fails)