-------------------------------------------------------------------------------
-- 16x16 RAM with synchronous write, and asynchronous read.
-- 
-- C       Clock
-- D[15:0] Bidirectional 16-bit data bus
-- A[3:0]  4-bit address
-- WE      Active-high write enable
-- DEN     Active-high data output enable
-------------------------------------------------------------------------------

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;

entity RAMB_1RW is
  port(
    D   : inout std_logic_vector(15 downto 0);
    ADR : in    std_logic_vector(3 downto 0);
    CLK : in    std_logic;
    WE  : in    std_logic;
    DEN : in    std_logic);
end entity;

architecture A of RAMB_1RW is
  type T_RAM is array(0 to 15) of std_logic_vector(15 downto 0);
  signal RAM  : T_RAM;
  signal IADR : integer range 0 to 15;
begin

  IADR <= to_integer(unsigned(ADR));

  D    <= RAM(IADR) when DEN = '1' else
          (others => 'Z');

  process(CLK) is
  begin
    if rising_edge(CLK) then
      if WE = '1' then
        RAM(IADR) <= D;
      end if;
    end if;
  end process;
end architecture;