FDSE is a D-type flip-flop with an active-high clock enable (CE), and a synchronous active-high set (S). S takes precedence over CE. The S and CE inputs are examined in priority order during the low-to-high transition of the clock (C) input. If S is asserted, Q is set to 1. Otherwise, if CE is asserted, Q is loaded with the data on the D input. Otherwise, Q retains its previous value.

Verilog

module FDSE(
  input S, CE, D, C, 
  output reg Q);

  always @(posedge C)
    if(S)
      Q <= 1;
    else if(CE)
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDSE is
  port (
    S, CE, D, C : in  std_logic;
    Q           : out std_logic);
end entity FDSE;

architecture A of FDSE is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if S = '1' then
        Q <= '1';
      elsif CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDSE(input S, CE, D, C, output Q)
   create_clock C
   [S, CE, D, C] -> [Q]
}

[1, 1, 0, .C] -> [1]      // set
[0, 0, 0, .C] -> [1]      // no CE; hold at 1
[0, 1, 0, .C] -> [0]      // CE; 1->0
[0, 0, 1, .C] -> [0]      // no CE; hold at 0
[0, 1, 1, .C] -> [1]      // CE; 0->1
[0, 1, 0, .C] -> [0]
[1, 1, 0, .C] -> [1]      // set