Array element selection

These two behavioural models are far simpler than the other mux8to1 models. However, perhaps surprisingly, XST produces exactly the same synthesis results as for any other model here. This style has perhaps not been used historically because of uncertainty over whether or not it is synthesisable; it would make sense to confirm this result with your own synthesiser before using this style.

This style also has an advantage in that metavalues in SEL are automatically propagated (for the Verilog code) or reported (for the VHDL code). The Verilog LRM requires I[SEL] to evaluate to X if SEL contains a metavalue. This is more pessimistic than either the conditional operator (Mux #1) or the logic-level examples (Mux #4), but is preferable in that it makes it more likely that the error will be detected. For the VHDL code, to_integer (from numeric_std) will report an error if SEL contains a metavalue, and will return 0.


module MUX8TO1(
    input [2:0] SEL, 
    input [7:0] I, 
    output      O);

   assign O = I[SEL];


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;               -- unsigned and to_integer

entity MUX8TO1 is
  port (
    SEL : in  unsigned(2 downto 0);
    I   : in  std_logic_vector(7 downto 0);
    O   : out std_logic);
end entity MUX8TO1;

architecture A of MUX8TO1 is
  O <= I(to_integer(SEL));
end architecture A;