VHDL selected signal assignment

This code uses a concurrent signal assignment, and is the concurrent equivalent of mux8to1_a2.vhd. It should produce identical results in synthesis. This version, however, is more concise, and doesn't require a correct sensitivity list. Note the use of the to_integer function to allow the case items to be specified as an integer (4 rather than "100", for example).


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;               -- unsigned and to_integer

entity MUX8TO1 is
  port (
    SEL : in  unsigned(2 downto 0);
    I   : in  std_logic_vector(7 downto 0);
    O   : out std_logic);
end entity MUX8TO1;

architecture A of MUX8TO1 is
  with to_integer(SEL) select
    O <= 
      I(0) when 0,
      I(1) when 1,
      I(2) when 2,
      I(3) when 3,
      I(4) when 4,
      I(5) when 5,
      I(6) when 6,
      I(7) when others;
end architecture A;