FDRSE is a D-type flip-flop with an active-high clock enable (CE), and synchronous active-high reset (R) and set (S) inputs. The R, S, and CE inputs are examined in priority order during the low-to-high transition of the clock (C) input. If R is asserted, Q is set to 0. Otherwise, if S is asserted, Q is set to 1. Otherwise, if CE is asserted, Q is loaded with the data on the D input. Otherwise, Q retains its previous value.

Verilog

module FDRSE(
  input R, S, CE, D, C, 
  output reg Q);

  always @(posedge C)
    if(R)
      Q <= 0;
    else if(S)
      Q <= 1;
    else if(CE)
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDRSE is
  port (
    R, S, CE, D, C : in  std_logic;
    Q              : out std_logic);
end entity FDRSE;

architecture A of FDRSE is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if R = '1' then
        Q <= '0';
      elsif S = '1' then
        Q <= '1';
      elsif CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDRSE(input R, S, CE, D, C, output Q)
   create_clock C
   [R, S, CE, D, C] -> [Q]
}

[1, 0, 1, 1, .C] -> [0]       // sync reset
[0, 1, 1, 0, .C] -> [1]       // sync set
[0, 0, 0, 0, .C] -> [1]       // no CE, holds at 1
[0, 0, 1, 0, .C] -> [0]       // CE, 1->0
[0, 0, 0, 1, .C] -> [0]       // no CE, holds at 0
[0, 0, 1, 1, .C] -> [1]       // CE, 0->1
[1, 1, 1, 1, .C] -> [0]       // sync reset, overrides S