The source files are tut10.tv, and mac1.v or mac1.vhd.

The previous exercises all used a default pipeline level (of 1) when checking clocked vectors; the statement [A, B] -> [C] is actually equivalent to [A, B] ->1 [C]. When using the default pipeline level, the drive statement outputs are tested immediately after the first clock edge. This is suitable for simple tests, but can greatly complicate the testing of pipelined hardware. tut10.tv tests a pipelined MAC module, using drive statements of the form [A, B] ->n [C]. This statement confirms that the output is equal to C on the nth clock edge after the inputs have been applied.

The expected output is:

  (Log) (2590 ns) 257 vectors executed (257 passes, 0 fails)