This article isn't a tutorial on writing HDL code, but it may be helpful to review some basic areas before proceeding:

1. Blocking or non-blocking assignments? If you're writing Verilog code, then you'll need to know the difference between the two, and when to use each type of assignment.
2. Synchronous or asynchronous resets? You'll need to decide in advance which sort of reset you should be using for your sequential (clocked) logic.
3. Coding Finite State Machines: one process or two?

Similarly, this article should not be used to compare VHDL and Verilog. The examples given here are far too simple to allow any meaningful comparison of the languages. However, if you're new to HDLs, you'll quickly notice that the Verilog code is more concise than the VHDL code, and you may conclude that Verilog is somehow "better" or easier to learn than VHDL. If so, you should read this.