/**
 * 16x16 RAM with synchronous write, and asynchronous read.
 * 
 * C       Clock
 * D[15:0] Bidirectional 16-bit data bus
 * A[3:0]  4-bit address
 * WE      Active-high write enable
 * DEN     Active-high data output enable
 */

module RAMB_1RW
   (inout  [15:0] D,
    input  [ 3:0] ADR,
    input 	  CLK, WE, DEN);

   reg [15:0] RAM[15:0];

   assign D = (DEN)? RAM[ADR] : {16{1'bz}};
 
   always @(posedge CLK)
     if(WE)
       RAM[ADR] <= D;

endmodule