If you're here to try to decide which language you should be learning, then one thing will be immediately obvious to you (and to anyone else): the Verilog code examples are generally much shorter than the VHDL examples. You might conceivably then come to the conclusion that you're going to find it easier to learn Verilog than VHDL, or that Verilog is in some way "better" because it is more concise. If so, then you'll need to think again.

The first thing that you need to consider is that you're comparing apples and oranges. The VHDL code uses packages, which makes it more flexible than the Verilog code. This accounts for the library and use clauses at the top of the source files. Secondly, VHDL has a mechanism that allows the interface to a device (the component and entity) to be specified independently of the implementation of that device (the specific architecture). The downside is that more typing is required in the source code. A subset of this functionality was introduced in Verilog-2001, but is less flexible, and does not separate interface from implementation.

However, having said that, there is no question that VHDL is overly verbose. It is dated and was designed as a general-purpose specification language, rather than as an electronic system simulation language. A dedicated 4-state logic type, for example, would have gone a long way towards reducing verbosity, but the designers preferred to use a general-pupose enumerated type. In its favour, however, it can be said that you can generally see VHDL's faults just by looking at the source code. Verilog's faults (and there are many) are generally subtle, hidden, confusing, and surprising.

Here's one quick tip on reducing VHDL verbosity. In any practical project, you are going to have hundreds, if not thousands, of lines of code which explicitly spell out std_logic_vector:

    signal MYSIG : std_logic_vector(39 downto 0);
  

The example code on this site all does this, but only because it has to be self-contained in a single source file. Never do this in a real project. Collect up all your bus widths, and explicitly subtype them in a project-wide package:

    package project_types is
       subtype SLV1024 is std_logic_vector(1023 downto 0);
       ...
       subtype SLV40   is std_logic_vector(39 downto 0);
       ...
       subtype SLV1    is std_logic_vector(0 downto 0);
       -- repeat for all unsigned/signed/integer range/etc subtypes
    end package project_types;
  

And now write your code as follows:

    use project_types.all;
    ...
    signal MYSIG : SLV40;