FDP is a D-type flip-flop with an asynchronous active-high preset (PRE). If PRE is asserted, the Q output is set to 1. The data on the D input is otherwise loaded to the Q output on the low-to-high transition of the clock (C) input.

Verilog

module FDP(
  input PRE, D, C, 
  output reg Q);

  always @(posedge C or posedge PRE)
    if(PRE)
      Q <= 1;
    else
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDP is
  port (
    PRE, D, C : in  std_logic;
    Q         : out std_logic);
end entity FDP;

architecture A of FDP is
begin
  process (C, PRE) is
  begin
    if PRE = '1' then
      Q <= '1';
    elsif rising_edge(C) then
      Q <= D;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDP(input PRE, D, C, output Q)
   create_clock C
   [PRE]       -> [Q]   // test async preset
   [PRE, D, C] -> [Q]   // test sync clocking
}

[1]         -> [1]      // async preset
[0,  0, .C] -> [0]
[0,  1, .C] -> [1]
[0,  0, .C] -> [0]
[1]         -> [1]      // async preset