mux8to1.tv

DUT {
   module MUX8TO1(input [2:0] SEL, input [7:0] I, output O);
   [SEL, I] -> [O];
}

main() {
   bit3 sel;
   bit8 data;
   for all data                     // cycles data from 0 to 255
      for all sel {                 // cycles sel from 0 to 7
         bit expected = data.(sel);
         [sel, data] -> [expected];
      }
}

This testbench can be used for all the mux8to1 code examples above. The expected output from the testbench is:

  (Log)   (20480 ns) 2048 vectors executed (2048 passes, 0 fails)