FD is a D-type flip-flop. The data on the D input is loaded to the Q output on the low-to-high transition of the clock (C) input.

Verilog

module FD(
  input D, C, 
  output reg Q);

  always @(posedge C)
    Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FD is
  port (
    D, C : in  std_logic;
    Q    : out std_logic);
end entity FD;

architecture A of FD is
begin
  process (C) is
  begin
    if rising_edge(C) then
      Q <= D;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FD(input D, C, output Q)  // 'reg' keyword is optional
   create_clock C
   [D, C] -> [Q]
}

[ 0, .C] -> [0]    // initialise
[ 1, .C] -> [1]    // 0 -> 1 transition
[ 0, .C] -> [0]    // 1 -> 0 transition