SR16RE is a 16-bit Serial In Parallel Out shift register, with a shift-left serial input (SLI), an active-high clock enable (CE), and an active-high synchronous reset (R). The R, CE, and SLI inputs are examined on the low-to-high transition of the clock (C). If R is asserted, Q is set to 0. Otherwise, if CE is asserted, SLI is loaded to Q[0], and the remaining bits of Q shift up (left) by one bit. Otherwise, Q retains its previous value.

Verilog

module SR16RE(
  input  R, CE, SLI, C,
  output reg [15:0] Q);

  always @(posedge C)
    if(R)
      Q <= 0;
    else if(CE)
      Q <= {Q[14:0], SLI};
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity SR16RE is
  port (
    R, CE, SLI, C : in     std_logic;
    Q             : buffer std_logic_vector(15 downto 0));
end entity SR16RE;

architecture A of SR16RE is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if R = '1' then
        Q <= (others => '0');
      elsif CE = '1' then
        Q(15 downto 1) <= Q(14 downto 0);
        Q(0) <= SLI;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module SR16RE(input R, CE, SLI, C, output[15:0] Q);
   create_clock C;
   [R, CE, SLI, C] -> [Q];
}

main() {
   int   i;
   bit16 test = 16'habcd;        // test input data; arbitrary
   [1, 1, 1, .C] -> [0];         // reset
   [0, 0, 1, .C] -> [0];         // check CE

   // shift in the test data, top bit first
   for(i = 15; i >= 0; i--) {
      bit1 din = test.(i);
      [0, 1, din, .C] -> [test >> i];
   }
}