FDR is a D-type flip-flop with a synchronous active-high reset (R). The Q output is loaded on the low-to-high transition of the clock (C) input. If R is asserted, Q is loaded with 0; it is otherwise loaded with the data on the D input.

Verilog

module FDR(
  input R, D, C, 
  output reg Q);

  always @(posedge C)
    if(R)
      Q <= 0;
    else
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDR is
  port (
    R, D, C : in  std_logic;
    Q       : out std_logic);
end entity FDR;

architecture A of FDR is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if R = '1' then
        Q <= '0';
      else
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDR(input R, D, C; output Q)
   create_clock C
   [R, D, C] -> [Q]
}

[1, 1, .C] -> [0];      // reset
[0, 1, .C] -> [1];
[0, 0, .C] -> [0];
[0, 1, .C] -> [1];
[1, 1, .C] -> [0];      // reset