Synthesis results

The 4 Verilog and 4 VHDL models were synthesised with Xilinx XST L.57, on ISE 11.3, targetting a Virtex-5 device (the XC5VLX30).

XST inferrred a one-bit 8-to-1 multiplexer for all the models apart from the logic-level ones (mux8to1_a4.v and mux8to1_a4.vhd). The RTL schematics for the logic-level models showed a gate-level description, while the RTL schematics for the other 6 models showed an 8:1 multiplexer.

The technology schematics for all 8 models were, however, identical. The schematics showed two LUT6 blocks, each of which handled 4 data inputs and 2 select inputs; the outputs of these two blocks were then combined in a MUXF7 (a 2:1 multiplexer), to produce the single-bit output.