Many of the models here have two versions: one with a synchronous reset, and one with an asynchronous reset. This leads to the obvious question of which version should be used. There is, unfortunately, no clear answer to this question.

In a complex design, there are always going to be corner cases which require an asynchronous reset; these might include, for example, clock generators, enables for tristate buses, and control signals which are driven externally.

You'll need to decide whether the rest of your logic should use a synchronous or an asynchronous reset, or possibly some combination of both. Keating and Bricaud cover this question (very) briefly, and appear to be in favour of synchronous resets; this is certainly the traditional solution. The paper by Cummings, Mills, and Golson covers the issues in much more detail.

Many FPGAs have a dedicated internal global asynchronous reset line; in principle, this frees up internal routing and improves timing (by keeping synchronous reset signals out of CLBs). On the face of it, then, it makes sense to use asynchronous resets exclusively in these devices. However, in practice, this net is generally unusable, since it is likely to be slow, and so cannot be synchronously de-asserted. The current Xilinx coding guidelines (UG901, p76) recommend using only synchronous resets. The paper by Ken Chapman may also be of interest. This isn't specifically concerned with the choice of an asynchronous or a synchronous reset, but makes the point that over-resetting an FPGA design can be counter-productive.

If you don't already know whether you should be using synchronous or asynchronous resets, and you don't have the time or the inclination to read the papers, then you should use synchronous resets. At some point, however, you're likely to find a problem.