The source files are tut6.tv, and counter1.v. This testbench writes to an internal signal in the DUT, to preload the state of the counter. Writes to internal signals are internally handled as 'force' operations; this testbench demonstrates the write and a subsequent 'release'. Force operations are not supported for VHDL in 2019.11, so there is no VHDL test.
The expected output is:
(Log) (220 ns) 22 vectors executed (21 passes, 0 fails)
Note that one of the vectors has a don't care in the output position, so the output isn't tested; this is why there are only 21 passes.