FDS is a D-type flip-flop with a synchronous active-high set (S). The Q output is loaded on the low-to-high transition of the clock (C) input. If S is asserted, Q is loaded with 1; it is otherwise loaded with the data on the D input.

Verilog

module FDS(
  input S, D, C, 
  output reg Q);

  always @(posedge C)
    if(S)
      Q <= 1;
    else
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDS is
  port (
    S, D, C : in  std_logic;
    Q       : out std_logic);
end entity FDS;

architecture A of FDS is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if S = '1' then
        Q <= '1';
      else
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDS(input S, D, C, output Q)
   create_clock C
   [S, D, C] -> [Q]
}

[1, 0, .C] -> [1]       // set
[0, 0, .C] -> [0]
[0, 1, .C] -> [1]
[0, 0, .C] -> [0]
[1, 0, .C] -> [1]       // set