FDCE is a D-type flip-flop with an active-high clock enable (CE), and an active-high asynchronous clear (CLR). If CLR is asserted, the Q output is set to 0. Otherwise, CE is examined during the low-to-high transition of the clock (C) input. If CE is asserted, the data on the D input is loaded to the Q output; otherwise, Q retains its previous value.

Verilog

module FDCE(
  input CLR, CE, D, C, 
  output reg Q);

  always @(posedge C or posedge CLR)
    if(CLR)
      Q <= 0;
    else if(CE)
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDCE is
  port (
    CLR, CE, D, C : in  std_logic;
    Q             : out std_logic);
end entity FDCE;

architecture A of FDCE is
begin
  process (C, CLR) is
  begin
    if CLR = '1' then
      Q <= '0';
    elsif rising_edge(C) then
      if CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDCE(input CLR, CE, D, C, output Q)
   create_clock C
   [CLR, CE, D]    -> [Q]  // test async reset
   [CLR, CE, D, C] -> [Q]  // test sync operation
}

[1, .X, .X] -> [0]         // async reset

[0, 1,  1, .C] -> [1]      // clock to 1
[0, 0, .X, .C] -> [1]      // output remains at 1
[0, 1,  0, .C] -> [0]      // clock to 0
[0, 0, .X, .C] -> [0]      // output remains at 0