FDE is a D-type flip-flop with an active-high clock enable (CE). The CE input is examined on the low-to-high transition of the clock (C) input. If it is asserted, the data on the D input is loaded to Q; otherwise, Q retains its previous value.

Verilog

module FDE(
   input CE, D, C, 
   output reg Q);

   always @(posedge C)
     if(CE)
       Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDE is
  port (
    CE, D, C : in  std_logic;
    Q        : out std_logic);
end entity FDE;

architecture A of FDE is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDE(input CE, D, C, output Q)
   create_clock C
   [CE, D, C] -> [Q]
}

[1, 1, .C] -> [1]       // load 1
[0, 0, .C] -> [1]       // hold if CE low
[1, 0, .C] -> [0]       // load 0
[0, 1, .C] -> [0]       // hold if CE low