/* ----------------------------------------------------------------------------
 *
 * tut10.tv
 *
 * The previous examples have all used a default pipeline level (of 1) when
 * checking clocked vectors; the statement '[a,b] -> [c]' is actually
 * equivalent to '[a,b] ->1 [c]'. This code checks the pipelined MAC unit in
 * mac1.v[hd]. mac1.v[hd] is actually behavioural code, for simplicity, and
 * has a parameter which defines the pipeline level. This code sets the
 * parameter ('stages') to PL, which is defined here as 3. The required
 * pipeline level can, in general, be a variable.
 *
 * Note that '_StrictChecking' is set to 0 to set the minimum level of
 * typechecking, and 'i', 'j', and 'sum' are all implicit 32-bit
 * variables. This code works only because the two loops do not allow i and j
 * to go above 15, and an explicit 8-bit multiply operator is used. See
 * tut11.tv for a safer and more compact version.
 * ------------------------------------------------------------------------- */

#pragma _StrictChecking 0           // default is 1
#define PL 3

DUT {
   module MAC1
      @(.stages(PL))
       (input  RST, CLK,
        input  [3:0] A, B,
        output [9:0] Q);

   [RST, CLK, A, B] -> [Q];
   create_clock CLK;
}

main() {
   sum = 0;

   [1, .C, -, -] ->PL [sum];        // check accumulator reset to 0
   for(i=0; i<16; i++)
      for(j=0; j<16; j++) {
         sum += (i *$8 j);
         [0, .C, i, j] ->PL [sum];  // check MAC operation
      }
}

// ----------------------------------- EOF ------------------------------------