-------------------------------------------------------------------------------
-- A behavioural model of a pipelined MAC unit. The two 4-bit inputs are
-- multiplied in an 8-bit multiplier, with the result added to a 10-bit
-- accumulator. The number of pipe stages is set by the 'stages' parameter,
-- which defaults to 1.
-- 
-- RST    Synchronous reset
-- C      Clock
-- A[3:0] Data Input
-- B[3:0] Data Input
-- Q[9:0] Accumulator output
-------------------------------------------------------------------------------

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;

entity MAC1 is
  generic(stages : integer := 1);
  port(
    RST : in  std_logic;
    CLK : in  std_logic;
    A   : in  std_logic_vector(3 downto 0);
    B   : in  std_logic_vector(3 downto 0);
    Q   : out std_logic_vector(9 downto 0));
end entity MAC1;

architecture A of MAC1 is
  type T_PIPE is array(0 to stages-1) of unsigned(9 downto 0);
  signal SUM : T_PIPE;
begin

  Q <= std_logic_vector(SUM(stages-1));

  process(CLK) is
    variable MUL : unsigned(7 downto 0);
  begin
    if rising_edge(CLK) then
      for i in stages-1 downto 1 loop
        SUM(i) <= SUM(i-1);
      end loop;

      if RST = '1' then
        SUM(0) <= (others => '0');
      else
        MUL    := unsigned(A) * unsigned(B);
        SUM(0) <= SUM(0) + ("00" & MUL);
      end if;
    end if;
  end process;
end architecture A;