/** * 4-bit Up Counter with synchronous load from primary input * * C Clock * SLOAD Synchronous Load (active High) * D[3:0] Data Input * Q[3:0] Data Output */ module Count4USL (input C, SLOAD, input [3:0] D, output [3:0] Q); reg [3:0] count; always @(posedge C) if(SLOAD) count <= D; else count <= count + 1; assign Q = count; endmodule