The source files are tut1.tv, and counter1.v or counter1.vhd. counter1 is a simple 4-bit counter, with a 4-bit data input, a synchronous load control, and a 4-bit count output. tut1.tv tests the operation of this counter.
tut1.tv is simply a test vector file, rather than a complete program with a 'main' function. It contains only a DUT declaration (which is copied directly from the module declaration in counter1.v), and a list of test vectors. This is all that's allowed in a "test vector file"; you cannot have functions, or declare variables. The DUT inputs must be driven with constant values, and the outputs must be tested against constant values. This form of testbench is generally suitable only for relatively simple tests.
Note that the module declaration can only be copied directly from the Verilog source if it is a "new style" (Verilog-2001) declaration, and it does not contain a parameter list. This is explained in detail in the LRM.
The expected output is
(Log) (180ns) 18 vectors executed (18 passes, 0 fails)
note that the clock declaration uses a default waveform, with a period of 10ns, so the test completes at 180ns.