MaiaEDA

Latest Release: 2021.4

Example 1 Example 2 Example 3 Example 4 Self-checking code Manual testing History

Supported simulators Unit test framework Downloads Contact Tutorial

Exercise 1 Exercise 2 Exercise 3 Exercise 4 Exercise 5 Exercise 6 Exercise 7 Exercise 8 Exercise 9 Exercise 10 Exercise 11 Exercise 12 Exercise 13 Exercise 14 Exercise 15 Exercise 16 Automation FIFO test

Introduction Maia and C DUT testing General Constants Functions Control flow Type system Variables Operators Arrays Structures Streams K-maps Object attributes

Simulator selection Internationalisation Testing VHDL DUTs Network simulation FAQs

Unit Testing TDD Other Verification HDL coding styles

Introduction Coding issues

Blocking vs. NBA Sync vs. async resets FSM coding styles Verilog vs. VHDL

FD FDE FDC FDCE FDP FDPE FDCP FDCPE FDR FDRE FDS FDSE FDRS FDRSE

Mux #1 Mux #2 Mux #3 Mux #4 Mux #5 Testbench Synthesis

Latches Shift registers FSMs

Style #1 Style #2 Style #3 Style #4 Style #5

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