Declared module port and signal names are simply external variables, like any other external variables. The drive statement gives a convenient mechanism for driving and testing these variables, but the tests can be carried out manually if necessary. The ability to read DUT outputs allows testbenches to be 'reactive'; in other words, the testbench can change its control flow, depending on the current state of the DUT. Note in particular the use of the _passCount, _failCount, and _timeNow internal variables. The wait statement can also be used to explicitly advance time.
The expected output is:
(tut9.tv, line 55: 17.5 ns) Ok (Log) (52.5 ns) 8 vectors executed (1 passes, 0 fails)
Note that the pass count is only 1; this is because the code explicitly
increments _passCount once. The pass and fail counts are normally
maintained internally, and are incremented automatically by drive
statements. In tut9.tv, testing is carried out explicitly by
using assert statements. The testbench will, be default, terminate
after an assertion failure; this behaviour may be changed by setting
the rte argument to either rtv or mtv (run
mtv -h for details).