FDRE is a D-type flip-flop with an active-high clock enable (CE), and a synchronous active-high reset (R). R takes precedence over CE. The R and CE inputs are examined in priority order during the low-to-high transition of the clock (C) input. If R is asserted, Q is set to 0. Otherwise, if CE is asserted, Q is loaded with the data on the D input. Otherwise, Q retains its previous value.

Verilog

module FDRE(
  input R, CE, D, C, 
  output reg Q);

  always @(posedge C)
    if(R)
      Q <= 0;
    else if(CE)
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDRE is
  port (
    R, CE, D, C : in  std_logic;
    Q           : out std_logic);
end entity FDRE;

architecture A of FDRE is
begin
  process (C) is
  begin
    if rising_edge(C) then
      if R = '1' then
        Q <= '0';
      elsif CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDRE(input R, CE, D, C, output Q)
   create_clock C
   [R, CE, D, C] -> [Q]
}

[1,  1,  1, .C] -> [0]    // reset; overrides CE
[0,  0,  1, .C] -> [0]    // no CE; hold at 0
[0,  1,  1, .C] -> [1]    // 0->1
[0,  0,  0, .C] -> [1]    // no CE; hold at 1
[0,  1,  0, .C] -> [0]    // 1->0
[0,  0,  1, .C] -> [0]    // no CE; hold at 0
[0,  1,  1, .C] -> [1]    // 0->1
[1, .X, .X, .C] -> [0]    // reset