FDPE is a D-type flip-flop with an active-high clock enable (CE), and an active-high asynchronous preset (PRE). If PRE is asserted, the Q output is set to 1. Otherwise, CE is examined during the low-to-high transition of the clock (C) input. If CE is asserted, the data on the D input is loaded to the Q output; otherwise, Q retains its previous value.

Verilog

module FDPE(
    input PRE, CE, D, C, 
    output reg Q);

   always @(posedge C or posedge PRE)
     if(PRE)
       Q <= 1;
     else if(CE)
       Q <= D;
endmodule

VHDL

entity FDPE is
  port (
    PRE, CE, D, C : in  std_logic;
    Q             : out std_logic);
end entity FDPE;

architecture A of FDPE is
begin
  process (C, PRE) is
  begin
    if PRE = '1' then
      Q <= '1';
    elsif rising_edge(C) then
      if CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDPE(input PRE, CE, D, C, output Q)
   create_clock C
   [PRE]           -> [Q]  // test async preset
   [PRE, CE, D, C] -> [Q]  // test sync operation
}

[1]           -> [1]       // async preset
[0, 1, 0, .C] -> [0]       // clock to 0
[0, 0, 1, .C] -> [0]       // output remains at 0
[0, 1, 1, .C] -> [1]       // clock to 1
[0, 0, 0, .C] -> [1]       // output remains at 1
[0, 1, 0, .C] -> [0]       // clock to 0
[0, 0, 1, .C] -> [0]       // output remains at 0
[1]           -> [1]       // async preset