FDCPE is a D-type flip-flop with an active-high clock enable (CE), and active-high asynchronous clear (CLR) and preset (PRE) inputs. CLR takes precedence over PRE. If CLR is asserted, the Q output is set to 0. Otherwise, if PRE is asserted, the Q output is set to 1. Otherwise, the CE input is examined during the low-to-high transition of the clock (C) input. If CE is asserted, the data on the D input is loaded to Q; Q otherwise retains its previous value.

Verilog

(Error)      (D100) 'fdcpe.tv', line 10, 24 ns: 'Q': expected 'b1; got 'b0
(Error)      (D100) 'fdcpe.tv', line 11, 34 ns: 'Q': expected 'b1; got 'b0
(Error)      (D100) 'fdcpe.tv', line 13, 49 ns: 'Q': expected 'b1; got 'b0
(Log)        (80 ns) 8 vectors executed (5 passes, 3 fails)

module FDCPE(
  input CLR, PRE, CE, D, C, 
  output reg Q);

  always @(posedge C or posedge CLR or posedge PRE)
    if(CLR)
      Q <= 0;
    else if(PRE)
      Q <= 1;
    else if(CE)
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDCPE is
  port (
    CLR, PRE, CE, D, C : in  std_logic;
    Q                  : out std_logic);
end entity FDCPE;

architecture A of FDCPE is
begin
  process (C, CLR, PRE) is
  begin
    if CLR = '1' then
      Q <= '0';
    elsif PRE = '1' then
      Q <= '1';
    elsif rising_edge(C) then
      if CE = '1' then
        Q <= D;
      end if;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDCPE(input CLR, PRE, CE, D, C, output Q)
   create_clock C
   [CLR, PRE]           -> [Q]   // test async clear/preset
   [CLR, PRE, CE, D, C] -> [Q]   // test sync operation
}

[1, .X] -> [0]                   // async clear, takes precedence over preset
[1,  1] -> [0]                   // assert preset, output unchanged
[0,  1] -> [1]                   // release clear, output sets to 1
[0,  0] -> [1]                   // release preset, output holds at 1

[0, 0, 0, 0, .C] -> [1]          // output remains at 1
[0, 0, 1, 0, .C] -> [0]          // clock to 0
[0, 0, 0, 1, .C] -> [0]          // output remains at 0
[0, 0, 1, 1, .C] -> [1]          // clock to 1