FDC is a D-type flip-flop with an asynchronous active-high clear (CLR). If CLR is asserted, the Q output is set to 0. The data on the D input is otherwise loaded to the Q output on the low-to-high transition of the clock (C) input.

Verilog

module FDC(
  input CLR, D, C, 
  output reg Q);

  always @(posedge C or posedge CLR)
    if(CLR)
      Q <= 0;
    else
      Q <= D;
endmodule

VHDL

library IEEE;
use IEEE.std_logic_1164.all;

entity FDC is
  port (
    CLR, D, C : in  std_logic;
    Q         : out std_logic);
end entity FDC;

architecture A of FDC is
begin
  process (C, CLR) is
  begin
    if CLR = '1' then
      Q <= '0';
    elsif rising_edge(C) then
      Q <= D;
    end if;
  end process;
end architecture A;

Testbench

DUT {
   module FDC(input CLR, D, C, output Q)
   create_clock C
   [CLR, D] -> [Q]      // test async reset
   [CLR, D, C] -> [Q]   // test sync clocking
}

[1, .X] -> [0]          // async reset

[0,  1, .C] -> [1]      // 0->1 transition
[0,  0, .C] -> [0]      // 1->0 transition