/* ----------------------------------------------------------------------------
 *
 * tut7.v
 *
 * This code is identical to tut6.v, except that the 'count' signal in the DUT
 * is now declared as an inout (bidirectional). This has no practical purpose
 * in this case, but does demonstrate that both external ports and internal
 * signals can be bidirectional. Note that the internal signal is also read
 * back during the counter force/preload, so this testbench reports two more
 * passes than tut6.v.
 *
 * ------------------------------------------------------------------------- */

DUT {
   module Count4USL              // copy the HDL module declaration here
       (input  C, SLOAD,
        input  [3:0] D,
        output [3:0] Q);

   create_clock C;               // declare the clock

   signal(inout [3:0] count);    // an internal signal in the DUT

   [C, SLOAD, D] -> [Q];         // DUT port vector declaration
   [C, count] -> [count, Q];     // vectors for force/preload
}

void main() {
   [.C, 1, 0]  -> [0];           // clear the counter

   // count up 16 times
   var4 i = 0;
   do
      [.C, 0, .X] -> [++i];
   while(i != 0);

   [.C, -, -]  -> [1];           // check that we're back at 1

   // the upcoming preload is on the 'wrong' side of the clock, and so
   // glitches the output; we need to put in a don't care before it (see
   // the FAQ)
   [.C, -, -]  -> [-];           // don't check the output; it's glitching

   [.C, 10]    -> [10, 10];      // preload to count 10
   [.C, .R]    -> [11, 11];      // release and count
   [.C, 0, .X] -> [12];          // make sure that we can still count
}

// ----------------------------------- EOF ------------------------------------