/* ----------------------------------------------------------------------------
 *
 * tut12.tv
 *
 * This test uses 3 'trigger functions', in addition to 'main'. The main
 * routine generates 32 clock pulses to a 4-bit up-counter, and confirms that
 * the Q output cycles twice through 0 to 15.
 *
 * 'main' also executes 3 trigger statements. These statements post the
 * trigger functions for later execution, if and when the associated trigger
 * conditions become valid. The trigger conditions may be arbitrarily complex,
 * but in this case:
 *
 * - 'trigFunctionA' will be executed whenever Q is 9
 * - 'trigFunctionB' is executed once, when Q is 3 on the second iteration
 * - 'trigFunctionC' is executed once, when Q is 4 on the first iteration
 *
 * 'main' executes 32 vectors. 'trigFunctionA' executes 3 vectors on each
 * iteration, and 'trigFunctionB' and 'trigFunctionC' each execute a total of
 * 1 vector. This test therefore runs a total of 40 vectors.
 *
 * ------------------------------------------------------------------------- */

#pragma _StrictChecking 0

DUT {
   module Count4USL (               // copy the HDL module declaration here
      input C, SLOAD,
      input  [3:0] D,
      output [3:0] Q);

   // the clock has a period of 8ns, with a rising edge after 2ns, and the
   // falling edge 3ns later
   create_clock C -period 8 -waveform {2, 5};

   // declare all the drive statements that we use below
   [C, SLOAD, D] -> [Q];
   @trigFunctionA [C] -> [Q];
   @trigFunctionB [C] -> [Q];
   @trigFunctionC [C] -> [Q];
}

main() {

   // this 'when all' trigger automatically re-arms, so 'trigFunctionA' is
   // triggered twice
   trigger trigFunctionA() when all Q == 9;

   [.C, 1, 0]  -> [0];              // preload Q to 0
   for(i=1; i<4; i++)
      [.C, 0, .X] -> [i];           // 3 more clock cycles

   // Q is now 3, so we miss the 'trigFunctionB' trigger condition, but we
   // catch the 'trigFunctionC' condition
   trigger trigFunctionB() when Q == 3;
   trigger trigFunctionC() when Q == 4;

   for(; i<32; i++)
      [.C, 0, .X] -> [i & 15];      // 28 more clock cycles
}

/**
 * 'trigFunctionA' is triggered twice, when we sample 9 at the DUT outputs.
 * we check that the Q output cycles to 10, 11, and 12 on the next 3 clocks.
 * These tests of course duplicate the tests in 'main'.
 */
@trigFunctionA() {
   report("trigFunctionA: Q is %u; time %t\n", Q, _timeNow);
   ->[10];
   ->[11];
   ->[12];
}

/**
 * 'trigFunctionB' should trigger only on the second iteration; the trigger is
 * missed the first time around. We test that Q increments on the next clock
 * edge (this again duplicates the test in 'main').
 */
@trigFunctionB() {
   report("trigFunctionB: Q is %u; time %t\n", Q, _timeNow);
   var32 q = Q;
   ->[q+1];
}

/**
 * 'trigFunctionC' is triggered once, when the Q output is sampled equal to 4,
 * on the first iteration. We test that Q increments on the next clock edge
 * (this again duplicates the test in 'main').
 */
@trigFunctionC() {
   report("trigFunctionC: Q is %u; time %t\n", Q, _timeNow);
   var32 q = Q;
   ->[++q];
}

// ----------------------------------- EOF ------------------------------------