/* ----------------------------------------------------------------------------
 *
 * tut11.tv
 *
 * A second version of tut10.tv, in which the '_StrictChecking' pragma is
 * left at its default level of 1. This disables implicit variables, and
 * enforces size checking on module ports. This is therefore a safer version
 * of tut10.tv, and requires correctly-sized variables to be declared.
 *
 * This version also uses the 'for all' loop construct. This automatically
 * cycles though all the possible values of the loop index, starting at 0.
 * ------------------------------------------------------------------------- */

#define PL 3

DUT {
   module MAC1
      @(.stages(PL))
       (input  RST, CLK,
        input  [3:0] A, B,
        output [9:0] Q);

   [RST, CLK, A, B] -> [Q];
   create_clock CLK;
}

void main() {
   var4  ina = 0, inb = 0;       // 4-bit
   var10 sum = 0;                // 10-bit

   [1, .C, -, -] ->PL [sum];     // reset, check that the output clears
   for all ina
      for all inb
         [0, .C, ina, inb] ->PL [sum += (ina *$8 inb)];
}

// ----------------------------------- EOF ------------------------------------