/**
 * The Count4USL module from 'counter1.v', but with an error. The counter
 * rolls over at count 14, rather than count 15.
 * 
 * C      Positive-Edge Clock
 * SLOAD  Synchronous Load (active High)
 * D[3:0] Data Input
 * Q[3:0] Data Output
 */
module Count4USL
  (input  C, SLOAD,
   input  [3:0] D,
   output [3:0] Q);

   integer count;

   always @(posedge C)
     if(SLOAD)
       count <= D;
     else if(count == 14)
       count <= 0;
     else
       count <= count + 1;
   assign Q = count;
endmodule