DUT {
   module MAC1                      // declare the module interface...
      @(.stages(3))                 // ...just paste in the Verilog module
       (input  RST, CLK,            //    declaration (replacing '#' with '@')
        input  [3:0] A, B,
        output [9:0] Q);
   
   [RST, CLK, A, B] -> [Q];
   create_clock CLK;                // default timing
}

void main() {
   var4  a=0, b=0;                  // vars initialise to x
   var10 sum=4;
   [1, .C, -, -] ->3 [0];           // check that Q resets to 0 after 3 cycles
   [0, .C, 2, 2] ->3 [sum];         // sanity check: 2*2=4

   for(int i=0; i<16; i++) {
      for(int j=0; j<16; j++) {
         sum += (a *$8 b);
         [0, .C, a, b++] ->3 [sum]; // drive A and B, check that Q equals 'sum' 3 cycles later
      }
      ++a;
   }
}