/* ----------------------------------------------------------------------------
 *
 * tut6.v
 *
 * This testbench again tests the basic 4-bit counter. However, it now
 * declares an internal signal in the counter, and drives that signal (using a
 * force) to set the value of the counter. A special directive (.R) is
 * required to release the force operation. In this particular case, of
 * course, we could just the external data input to preload the counter, and a
 * force operation isn't necessary. However, the force is the basic mechanism
 * to preload any internal state into a DUT.
 *
 * The internal signal is declared with a signal declaration; the name(s) in
 * this declaration must match the names in the HDL code. Hierarchical names
 * may be used. The syntax of a signal declaration is the same as the syntax
 * of the module declaration. Internal signals may be declared as inputs (to
 * drive them), as outputs (to read them), or as inouts (to do both; see the
 * example in tut7.tv).
 *
 * Whenever you write to (drive) an internal signal you are using a 'force',
 * which overrides any existing value on that signal. To restore the internal
 * value of that signal you must explicitly 'release' it, by using the .R
 * directive.
 *
 * ------------------------------------------------------------------------- */

DUT {
   module Count4USL              // copy the HDL module declaration here
       (input  C, SLOAD,
        input  [3:0] D,
        output [3:0] Q);

   create_clock C;               // declare the clock

   signal(input [3:0] count);    // an internal signal in the DUT

   [C, SLOAD, D] -> [Q];         // DUT port vector declaration
   [C, count] -> [Q];            // vectors for force/preload
}

void main() {
   [.C, 1, 0]  -> [0];           // clear the counter

   // count up 16 times
   var4 i = 0;
   do
      [.C, 0, .X] -> [++i];
   while(i != 0);

   [.C, -, -]  -> [1];           // check that we're back at 1

   // the upcoming preload is on the 'wrong' side of the clock, and so
   // glitches the output; we need to put in a don't care before it (see
   // the FAQ)
   [.C, -, -]  -> [-];           // don't check the output; it's glitching

   [.C, 10]    -> [10];          // preload to count 10
   [.C, .R]    -> [11];          // release and count
   [.C, 0, .X] -> [12];          // make sure that we can still count
}

// ----------------------------------- EOF ------------------------------------