/* ----------------------------------------------------------------------------
 *
 * tut5.v
 *
 * Testbench for a 16-bit by 16-word memory. This is identical to tut4.tv,
 * except that we now declare an enable signal with 'create_enable'.
 *
 * The advantage of an enable signal is that the testbench can ensure that a
 * bidirectional signal is never driven at the same time by both the testbench
 * and the DUT. This saves some complexity in your testbench. If you don't use
 * create_enable, you must manually prevent contention yourself, by driving Z
 * data out of the testbench when necessary. If you use create_enable, the
 * testbench decides for itself when to drive Z, and overrides the actual data
 * that you specify in your test vector.
 *
 * ------------------------------------------------------------------------- */
 
#define SET_TESTDATA(x, y) \
   do {                    \
    x.(15:12) = y;         \
    x.(11: 8) = y .ROL 1;  \
    x.( 7: 4) = y .ROL 2;  \
    x.( 3: 0) = y .ROL 3;  \
   } while(0)

DUT {
   module RAMB_1RW
       (inout  [15:0] D, 
       input  [ 3:0] ADR,
       input  CLK, WE, DEN);

   create_clock CLK;

   [CLK, DEN, WE, ADR, D]; 
   [DEN, ADR, D] -> [D];

   /* the DUT drives D when DEN is 1, and tristates D when DEN is 0. However,
    * 'create_enable' creates a *testbench* enable signal: in other words, the
    * TB drives D to the DUT when DEN is 0, and tristates D when DEN is 1 */
   create_enable D(!DEN);
}

void main() {
   var4  a;                      // 4-bit address
   var16 d;                      // 16-bit data

   // if DEN is 0, the DUT is not driving, and the testbench is driving. check
   // that we can read back the testbench-driven data
   [0, -, 16`habcd] -> [16`habcd];

   /* setting DEN automatically turns off the testbench drivers, so it doesn't
    * matter what is specified on the testbench D output; it is
    * overridden. the testbench will read back whatever is on the DUT's D
    * output; this is currently X */
   [1, -, 16`habcd] -> [.X];

   int i;
   for(i=0, a=0; i<16; i++, a++) {
      SET_TESTDATA(d, a);
      [.C, 0, 1, a, d];
   }

   for(i=0, a=0; i<16; i++, a++) {
        SET_TESTDATA(d, a);
        [1, a, -] -> [d];          // .Z not required
   }
}

// ----------------------------------- EOF ------------------------------------