/* ----------------------------------------------------------------------------
 *
 * tut2.tv
 *
 * A test for a simple 4-bit up counter, with a synchronous load. We preload
 * 2, and count all the way round, back to 4, giving a total of 20 vectors.
 * This code is basically identical to tut1.v, except that the vectors are
 * enclosed in a function, and a for loop iterates through 16 vectors.
 *
 * Note that:
 *
 * 1 - functions are used; the test starts at main(), which calls test()
 *
 * 2 - Semicolon termination is therefore required after the test vectors
 *
 * 3 - the '_StrictChecking' pragma is set to 0, to give the minimum level
 *     of typechecking (or compiler interference, if you prefer to see it that
 *     way). See (4) and (5) below for what this means. In general, you should
 *     leave '_StrictChecking' at its default level of 1, although a level of
 *     0 can be useful for quick sanity-test checking.
 *
 * 4 - Setting '_StrictChecking' to 0 allows an implicitly-declared variable
 *     (i) to be used. This is a 4-state variable, and is created when it is
 *     first written to. It has a default size of 32 bits (see the
 *     '_DefaultWordSize' pragma).
 *
 * 5 - Setting '_StrictChecking' to 0 also allows us to test the 4-bit Q
 *     output against the unsized 'i'. The compiler doesn't complain about
 *     the size mismatch, and it only uses the bottom 4 bits of 'i' for the
 *     test.
 *
 * The 4-bit Q output is also tested agaist the unsized constant '2'. It is
 * always possible to test against simple unsized decimal constants, whatever
 * the value of '_StrictChecking'; this saves the hassle of constantly using
 * sized constants such as "4'd2", rather than simply '2'.
 *
 * See tut3.tv for a safer version, which leaves '_StrictChecking' at its
 * default value.
 * ------------------------------------------------------------------------- */

#pragma _StrictChecking 0  // defaults to 1

DUT {
   module Count4USL        // copy the HDL module declaration here
      (input  C, SLOAD,
       input  [3:0] D,
       output [3:0] Q)

   create_clock C          // declare the clock

   [C, SLOAD, D] -> [Q]    // drive declaration
}

test() {
   [.C, 1, 2]  -> [2];     // load 2, test against 2

   i = 2;                  // implicitly-declared variable, default size
   
   [.C, 0, .X] -> [++i];   // turn off SLOAD, test against 3
   [.C, -, -]  -> [++i];   // SLOAD and D retain their previous values

   for(i=0; i<16; i++)
      [.C, -, -] -> [i+5];
}

main() {
   [.C, 0, -]  -> [.X];    // outputs unknown
   test();
}

// ----------------------------------- EOF ------------------------------------