/* ----------------------------------------------------------------------------
 *
 * tut1.tv
 *
 * A test for a simple 4-bit up counter, with a synchronous load. We preload
 * 2, and count all the way round, back to 2, giving 18 vectors.
 *
 * Note that:
 *
 * 1 - The DUT's Verilog module declaration is copied with no changes. If the
 *     DUT is VHDL, then the entity declaration should be translated into
 *     this form
 *
 * 2 - Semicolon statement termination is optional. However, If you're using
 *     a C mode for editing, the editor will probably require semicolons for
 *     correct statement indenting
 *
 * 3 - You cannot have both 'external' test vectors and functions; this form
 *     of test vector file is used only for simple tests. You cannot declare
 *     or use variables; you can only use constants in the test vectors.
 *     If you uncomment the 'main' function the compiler will complain.
 *
 * ------------------------------------------------------------------------- */

DUT {
   module Count4USL     // copy the module/entity declaration here
      (input  C, SLOAD,
       input  [3:0] D,
       output [3:0] Q)

   create_clock C       // declare the clock

   [C, SLOAD, D] -> [Q] // drive declaration
}

[.C, 0, -]  -> [.X]     // outputs unknown
[.C, 1, 2]  -> [2]      // preload 2
[.C, 0, .X] -> [3]      // turn off SLOAD; doesn't matter what D is driven with
[.C, -, -]  -> [4]      // SLOAD and D retain their previous values
[.C, -, -]  -> [5]
[.C, -, -]  -> [6]
[.C, -, -]  -> [7]
[.C, -, -]  -> [8]
[.C, -, -]  -> [9]
[.C, -, -]  -> [10]
[.C, -, -]  -> [11]
[.C, -, -]  -> [12]
[.C, -, -]  -> [13]
[.C, -, -]  -> [14]
[.C, -, -]  -> [15];    // semicolons are optional
[.C,  , -]  -> [0];     // rollover to 0. '-' is optional
[.C, -,  ]  -> [1];
[.C,,]      -> [2];     // complete one pass

// uncomment to get a syntax error...
// main() {}

// ----------------------------------- EOF ------------------------------------