/**
 * A behavioural model of a pipelined MAC unit. The two 4-bit inputs are
 * multiplied in an 8-bit multiplier, with the result added to a 10-bit
 * accumulator. The number of pipe stages is set by the 'stages' parameter,
 * which defaults to 1.
 * 
 * RST    Synchronous reset
 * C      Clock
 * A[3:0] Data Input
 * B[3:0] Data Input
 * Q[9:0] Accumulator output
 */

module MAC1
  (input  RST, CLK,
   input  [3:0] A, B,
   output [9:0] Q);

   parameter 	stages = 1;

   reg [7:0] 	mul;
   reg [9:0] 	sum[stages-1:0];
   integer 	i;

   always @(posedge CLK) begin
      for(i=stages-1; i>0; i = i-1)
	sum[i] = sum[i-1];

      if(RST)
	sum[0] = 0;
      else begin
	 mul = A * B;
	 sum[0] = sum[0] + mul;
      end
   end

   assign Q = sum[stages-1];
endmodule