`timescale 1 ns / 1 ns

module TFIFO_WRAPPER
   (input         CLK156,
    input         RST156,
    output reg    CLK250,
    output 	  FF,
    input 	  WREN,
    input [15:0]  DIN,
    output 	  EF,
    input 	  RDEN,
    output [15:0] DOUT);

   initial begin
      CLK250 = 0;
      forever
	 #2 CLK250 = !CLK250;
   end

   FIFO_16x31 U1
      (.rst   (RST156),
       .wr_clk(CLK156),
       .rd_clk(CLK250),
       .din   (DIN),
       .wr_en (WREN),
       .rd_en (RDEN),
       .dout  (DOUT),
       .full  (FF),
       .empty (EF));
endmodule