-------------------------------------------------------------------------------
-- 4-bit Up Counter with synchronous load from primary input
-- 
-- C      Clock
-- SLOAD  Synchronous Load (active High)
-- D[3:0] Data Input
-- Q[3:0] Data Output
-------------------------------------------------------------------------------

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;

entity Count4USL is
  port(
    C     : in  std_logic;
    SLOAD : in  std_logic;
    D     : in  std_logic_vector(3 downto 0);
    Q     : out std_logic_vector(3 downto 0));
end entity Count4USL;

architecture A of Count4USL is
  signal COUNT : unsigned(3 downto 0);
begin

  Q <= std_logic_vector(COUNT);

  process(C) is
  begin
    if rising_edge(C) then
      if SLOAD = '1' then
        COUNT <= unsigned(D);
      else
        COUNT <= COUNT + 1;
      end if;
    end if;
  end process;
end architecture A;