/** A simple 3-input, 1-output combinatorial model. The model implements the D output as this K-map: /- B -\ --------------- A | 1 | 0 | 1 | 1 | |---------------| | 0 | 1 | 0 | 1 | --------------- \- C -/ */ library ieee; use ieee.std_logic_1164.all; entity COMB3 is port( A : in std_logic; B : in std_logic; C : in std_logic; D : out std_logic); end entity; architecture A of COMB3 is begin D <= ( A and B and not C) or (not A and B and C) or ( A and not B ) or ( not B and not C); end architecture; /* ---------------------------------- EOF ---------------------------------- */