/* ----------------------------------------------------------------------------
 *     Copyright (c) 2000-2019, Nexus Electronics Ltd (www.nexus.co.uk)
 *                            All rights reserved
 *
 * Redistribution and use in source and derived forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in derived forms must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of Nexus Electronics Ltd. nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY NEXUS ELECTRONICS LTD. "AS IS" AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL NEXUS ELECTRONICS LTD. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGE.
 * ----------------------------------------------------------------------------
 * Title       : FIPS 800-20 known answer tests, 3DES, CBC and ECB modes
 * Project     : MAS
 * RCS ID      : 
 * $Id: des_kats.v,v 1.1 2001/01/16 18:09:46 el Exp $
 * ----------------------------------------------------------------------------
 * File        : des_kats.v
 * Author      : E.M. Lavelle
 * Company     : Nexus Electronics Ltd.
 * Last saved  : 
 * Version     : $Revision: 867 $
 * ----------------------------------------------------------------------------
 * Description :
 *
 * See the README file in this directory.
 *
 * If VERBOSE is predefined, then details of all passed tests will be 
 * displayed. if SKIP is defined, lots of vectors are skipped to allow fast 
 * sanity-check testing.
 * 
 * ----------------------------------------------------------------------------
 * Modification history:
 * Date        Version Author     Comment
 * 12/01/2001  0.1     EML        created
 *
 * ------------------------------------------------------------------------- */

//`define VERBOSE 1
//`define SKIP    1

`include "../rtl/3des_inc.v"	// register decodes

`timescale 1ns/1ps
`define PERIOD   37
`define PERIOD_2 18.5
`define TIMEOUT  92     // hardware should respond to DAV_H within 92 cycles

`define NTESTS 4
`define VPKAT  0	        // variable plaintext known answer test
`define VKKAT  1		// variable key known answer test
`define POKAT  2		// permutation operation known answer test
`define STKAT  3		// substitution table known answer test
`define MAX_NROWS 64	        // longest set of vectors: max(test_nrow)
`define MAX_NCOLS 4	        // max number of columns: max(test_ncol)

module des_ka_tests;

   // UUT signals
   reg         CLK, SRST_H, CBC_H, ENC3D_H, DAV_H;
   reg [2:0]   ADDR;
   reg [1:64]  DATAIN;
   wire        DRDY_H; 	 
   wire [1:64] DATAOUT;

   // test data structures
   integer      test_nrow[(`NTESTS-1):0];
   integer      test_ncol[(`NTESTS-1):0];
   reg [5*8 :1] test_name[(`NTESTS-1):0];
   reg [21*8:1] test_file[(`NTESTS-1):0];
   
   // initialise the test data structures
   initial
     begin: init
	// Variable Plaintext Known Answer Test
	test_nrow[`VPKAT] = 64;	                      // file has 64 rows,
	test_ncol[`VPKAT] = 3;	                      // each of 3 columns
	test_name[`VPKAT] = "VPKAT";                  // for printed messages
	test_file[`VPKAT] = "vectors/des_vpkat.dat";  // test vector file

	// Variable Key Known Answer Test
	test_nrow[`VKKAT] = 56;
	test_ncol[`VKKAT] = 3;
	test_name[`VKKAT] = "VKKAT";
	test_file[`VKKAT] = "vectors/des_vkkat.dat";

	// Permutation Operation Known Answer Test
	test_nrow[`POKAT] = 32;
	test_ncol[`POKAT] = 3;
	test_name[`POKAT] = "POKAT";
	test_file[`POKAT] = "vectors/des_pokat.dat";

	// Substitution Table Known Answer Test
	test_nrow[`STKAT] = 19;
	test_ncol[`STKAT] = 4;
	test_name[`STKAT] = "STKAT";
	test_file[`STKAT] = "vectors/des_stkat.dat";
     end
   
   // instantiate the UUT
   triple_des UUT(CLK, SRST_H, CBC_H, ENC3D_H, DAV_H, ADDR, DATAIN,
		  DRDY_H, DATAOUT);

   // initialise the clock, generate the sync reset on the first clock cycle
   initial begin
      CLK <= 0;
      SRST_H <= 1;
      #`PERIOD
	SRST_H <= 0;
   end
   
   // clock generator
   always @(CLK)
     #`PERIOD_2 CLK <= ~CLK;

   initial
     begin: all_tests
	// test data: the data file is read into vectors, rather than arrays,
	// since it's required as a task parameter
	reg [1:64*`MAX_NROWS] key_vec;
	reg [1:64*`MAX_NROWS] plain_vec;
	reg [1:64*`MAX_NROWS] cipher_vec;
	integer test_id;

	#`PERIOD;		// wait till first CLK falling edge

	for(test_id=0; test_id<`NTESTS; test_id=test_id+1) begin

	   $display("%s: CBC mode, encode test:", test_name[test_id]);
	   CBC_H   <= 1;		// CBC mode, encode
	   ENC3D_H <= 1;
	   read_data(test_id, key_vec, plain_vec, cipher_vec);
	   do_fips  (test_id, key_vec, plain_vec, cipher_vec);

	   $display("%s: CBC mode, decode test:", test_name[test_id]);
	   CBC_H   <= 1;		// CBC mode, decode
	   ENC3D_H <= 0;
	   read_data(test_id, key_vec, plain_vec, cipher_vec);
	   do_fips  (test_id, key_vec, cipher_vec, plain_vec);

	   $display("%s: ECB mode, encode test:", test_name[test_id]);
	   CBC_H   <= 0;		// ECB mode, encode
	   ENC3D_H <= 1;
	   read_data(test_id, key_vec, plain_vec, cipher_vec);
	   do_fips  (test_id, key_vec, plain_vec, cipher_vec);

	   $display("%s: ECB mode, decode test:", test_name[test_id]);
	   CBC_H   <= 0;		// ECB mode, decode
	   ENC3D_H <= 0;
	   read_data(test_id, key_vec, plain_vec, cipher_vec);
	   do_fips  (test_id, key_vec, cipher_vec, plain_vec);

	   $display("%s test complete.", test_name[test_id]);
	end // for all tests
	
	$finish;
     end
   
   /* ------------------------------------------------------------------------
    * do_fips
    * apply the keys, plaintext, and ciphertext to the UUT, wait for
    * the result, and check it. the input data turns up as a single
    * vector, and the required test data must be extracted from it
    * ---------------------------------------------------------------------- */
   task do_fips;
      input test_id;
      input [1:64*`MAX_NROWS] key_data, inp_data, chk_data;
     
      integer test_id;
      integer i, j, passcount, failcount, vector_advance;
      reg [1:64] key_vec, inp_vec, chk_vec;

      begin

	 // quick sanity testing: only test every 16th vec if SKIP is defined
`ifdef SKIP
	 vector_advance = 16;
	 $display("(short test)");
`else
	 vector_advance = 1;
`endif

	 passcount = 0;
	 failcount = 0;
	 for(i=0; i<test_nrow[test_id]; i=i+vector_advance) begin

	    // reconstruct the current 64-bit vectors from within the entire
	    // test vector: this must be done bitwise, since we can't have
	    // expressions in ranges
	    for(j=1; j<=64; j=j+1) begin
	       key_vec[j] = key_data[(i*64)+j];
	       inp_vec[j] = inp_data[(i*64)+j];
	       chk_vec[j] = chk_data[(i*64)+j];
	    end

	    // strobe the test data into the UUT
	    load_reg(`REG_KEY1, key_vec);
	    load_reg(`REG_KEY2, key_vec);
	    load_reg(`REG_KEY3, key_vec);
	    load_reg(`REG_IV,   0);
	    load_reg(`REG_RUN,  inp_vec);
	    
	    // wait for the returned data
	    begin : wait_loop
	       while(1) begin
		  for(j=0; j<`TIMEOUT+8; j=j+1) begin
		     @(posedge CLK) begin
			if(DRDY_H)
			  disable wait_loop;
		     end
		  end
		  // we've had a timeout if we get here
		  $write("**%s: UUT failed to respond; terminating**\n",
			 test_name[test_id]);
		  $stop;
	       end		// while(1)
	    end			// wait_loop

	    // we've got data from the UUT: check it
	    if(DATAOUT == chk_vec) begin
	       passcount = passcount+1;
`ifdef VERBOSE
	       $display("      round %d Ok: key, in, out = %h, %h, %h",
			i, key_vec, inp_vec, DATAOUT);
`endif
	    end
	    else begin
	       failcount = failcount+1;
	       $display("      *ERROR, ROUND %d: K,I,O,E = %h, %h, %h, %h",
			i, key_vec, inp_vec, DATAOUT, chk_vec);
	    end
	    #`PERIOD_2;		// wait for the next clock falling edge
	 end	// for all input data

	 // test finished 
	 $display("%s: %d vectors passed, %d vectors failed",
		  test_name[test_id], passcount, failcount);
      end  // for(i=0;i<nrows;i++)
   endtask // do_fips

   /* ------------------------------------------------------------------------
    * load_reg
    * 
    * loads the UUT's input register, using the provided address and data.
    * note that the mode controls (ENC3D_H/CBC_H) are set up as static
    * inputs, and will be loaded in on a `REG_RUN load.
    * ---------------------------------------------------------------------- */
   task load_reg;
      input  [2:0]  address;
      input  [1:64] data;
      begin
	 DATAIN = data;
	 ADDR   = address;
	 DAV_H  = 1;	// strobe
	 #`PERIOD;	// clock in the data and clear the inputs
	 DATAIN = 0;
	 ADDR   = 0;
	 DAV_H  = 0;
      end
   endtask // load_reg

   /* ------------------------------------------------------------------------
    * read_data
    * 
    * get the test data corresponding to 'test_id'. the various arrays 
    * have to be converted to, and returned as, vectors, since verilog
    * doesn't allow array parameters to tasks. it also doesn't allow
    * expressions in ranges, so each bit must be individually assigned
    * ---------------------------------------------------------------------- */
   task read_data;
      input test_id;
      output [1:64*`MAX_NROWS] key_vec;
      output [1:64*`MAX_NROWS] plain_vec;
      output [1:64*`MAX_NROWS] cipher_vec;

      integer test_id;
      integer i,j;
      reg [1:64] memory[0:(`MAX_NROWS*`MAX_NCOLS)-1]; // data read from file
      reg [1:64] key, plain, cipher;              // reqd words on each line
      begin

	 $readmemh(test_file[test_id], memory); // read in the test data 
	 for(i=0; i<test_nrow[test_id]; i=i+1) begin

	    // VPKAT: columns are test number, plain, cipher, with a fixed key
	    if(test_id == `VPKAT) begin
	       key    = 64'h0101010101010101;
	       plain  = memory[(i*test_ncol[test_id])+1];
	       cipher = memory[(i*test_ncol[test_id])+2];
	    end

	    // VKKAT: columns are test number, key, cipher, with fixed plain
	    else if(test_id == `VKKAT) begin
	       key    = memory[(i*test_ncol[test_id])+1];
	       plain  = 0;
	       cipher = memory[(i*test_ncol[test_id])+2];
	    end

	    // POKAT: columns are test number, key, cipher, with fixed plain
	    else if(test_id == `POKAT) begin
	       key    = memory[(i*test_ncol[test_id])+1];
	       plain  = 0;
	       cipher = memory[(i*test_ncol[test_id])+2];
	    end

	    // STKAT: columns are test number, key, plain, cipher
	    else if(test_id == `STKAT) begin
	       key    = memory[(i*test_ncol[test_id])+1];
	       plain  = memory[(i*test_ncol[test_id])+2];
	       cipher = memory[(i*test_ncol[test_id])+3];
	    end

	    // we've now read (or created) 3 64-bit registers from entries
	    // in the current test file. these regs are now bitwise decomposed
	    // and inserted into the corresponding output vector
	    for(j=1; j<=64; j=j+1) begin            // for each bit 
	       key_vec   [(i*64)+j] = key   [j];
	       plain_vec [(i*64)+j] = plain [j];
	       cipher_vec[(i*64)+j] = cipher[j];
	    end	 // for all bits of each data word
	 end	 // for all rows in the data file
      end
   endtask       // read_data
   
endmodule // des_ka_tests

/*----------------------------------- EOF -----------------------------------*/