DUT {                            // declare the Device Under Test
   module reg4                   // can paste in the Verilog declaration directly
     (input  CLK,
      input  [3:0] D,
      output [3:0] Q);

   create_clock CLK;             // declare any clocks to be used (default timing)
   [CLK];                        // declare any drive statements to be used
}

void main() {
   for(bit4 i=0; i<10; i++) {
      D = i;                     // set up any inputs for the next clock edge
      [.C];                      // drive the clock, advance to the next OP
      if(Q == i) _passCount++;
      else       _failCount++;
   }
}