library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- unsigned and to_integer entity MUX8TO1 is port ( SEL : in unsigned(2 downto 0); I : in std_logic_vector(7 downto 0); O : out std_logic); end entity MUX8TO1; architecture A of MUX8TO1 is begin -- architecture A uses a concurrent (selected) signal assignment with to_integer(SEL) select O <= I(0) when 0, I(1) when 1, I(2) when 2, I(3) when 3, I(4) when 4, I(5) when 5, I(6) when 6, I(7) when others; end architecture A; architecture B of MUX8TO1 is begin -- architecture B uses a process with a case statement process(SEL, I) is begin case SEL is when "000" => O <= I(0); when "001" => O <= I(1); when "010" => O <= I(2); when "011" => O <= I(3); when "100" => O <= I(4); when "101" => O <= I(5); when "110" => O <= I(6); when others => O <= I(7); end case; end process; end architecture B; ------------------------------------------------------------------------------- -- The rest of the code is only required if you want to explicitly select the -- required multiplexer architecture (A or B). In normal circumstances, the -- last analysed architecture (in this case, B) is used. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity VHDL_TOP is port ( SEL : in unsigned(2 downto 0); I : in std_logic_vector(7 downto 0); O : out std_logic); end entity VHDL_TOP; architecture ONLY of VHDL_TOP is component MUX8TO1 is port ( SEL : in unsigned(2 downto 0); I : in std_logic_vector(7 downto 0); O : out std_logic); end component MUX8TO1; begin U1 : MUX8TO1 port map (SEL, I, O); end architecture ONLY; configuration VHDL_CONFIG of VHDL_TOP is for ONLY for U1 : MUX8TO1 use entity work.MUX8TO1(A); end for; end for; end configuration VHDL_CONFIG;