DUT {
   module VHDL_CONFIG (input [2:0] SEL, input [7:0] I, output O);
   [SEL, I] -> [O];
}

void main() {
   bit3 sel;
   bit8 data;
   for all data                     // cycles data from 0 to 255
      for all sel {                 // cycles sel from 0 to 7
         bit expected = data.(sel); // or data >> sel
         [sel, data] -> [expected];
      }
}